Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying solely on radiation-hardened technologies is extremely expensive, and developing inflexible architectural and microarchitectural modifications to introduce modular redundancy within a system leads to significant area increase and performance degradation. To mitigate the overheads of traditional radiation hardening and modular redundancy approaches, we present a novel Hybrid Modular Redundancy (HMR) approach, a redundancy scheme that features a cluster of RISC-V processors with a flexible on-demand dual-core and triple-core lockstep grouping of computing cores with runtime split-lock capabilities. Further, we propose two recovery approaches, software-based and hardware-based, trading off performance and area overhead. Running at 430 MHz, our fault-tolerant cluster achieves up to 1160 MOPS on a matrix multiplication benchmark when configured in non-redundant mode and 617 and 414 MOPS in dual and triple mode, respectively. A software-based recovery in triple mode requires 363 clock cycles and occupies 0.612 mm2, representing a 1.3% area overhead over a non-redundant 12-core RISC-V cluster. As a high-performance alternative, a new hardware-based method provides rapid fault recovery in just 24 clock cycles and occupies 0.660 mm2, namely ~9.4% area overhead over the baseline non-redundant RISC-V cluster. The cluster is also enhanced with split-lock capabilities to enter one of the redundant modes with minimum performance loss, allowing execution of a mission-critical or a performance section, with <400 clock cycles overhead for entry and exit. The proposed system is the first to integrate these functionalities on an open-source RISC-V-based compute device, enabling finely tunable reliability vs. performance trade-offs

A High-performance, Energy-efficient Modular DMA Engine Architecture

Data transfers are essential in today's computing systems as latency and complex memory access patterns are increasingly challenging to manage. Direct memory access engines (DMAEs) are critically needed to transfer data independently of the processing elements, hiding latency and achieving high throughput even for complex access patterns to high-latency memory. With the prevalence of heterogeneous systems, DMAEs must operate efficiently in increasingly diverse environments. This work proposes a modular and highly configurable open-source DMAE architecture called intelligent DMA (iDMA), split into three parts that can be composed and customized independently. The front-end implements the control plane binding to the surrounding system. The mid-end accelerates complex data transfer patterns such as multi-dimensional transfers, scattering, or gathering. The back-end interfaces with the on-chip communication fabric (data plane). We assess the efficiency of iDMA in various instantiations: In high-performance systems, we achieve speedups of up to 15.8x with only 1 % additional area compared to a base system without a DMAE. We achieve an area reduction of 10 % while improving ML inference performance by 23 % in ultra-low-energy edge AI systems over an existing DMAE solution. We provide area, timing, latency, and performance characterization to guide its instantiation in various systems.Comment: 14 pages, 14 figures, accepted by an IEEE journal for publicatio

Schlafen 12 restricts HIV-1 latency reversal by a codon-usage dependent post-transcriptional block in CD4+ T cells

Latency is a major barrier towards virus elimination in HIV-1-infected individuals. Yet, the mechanisms that contribute to the maintenance of HIV-1 latency are incompletely understood. Here we describe the Schlafen 12 protein (SLFN12) as an HIV-1 restriction factor that establishes a post-transcriptional block in HIV-1-infected cells and thereby inhibits HIV-1 replication and virus reactivation from latently infected cells. The inhibitory activity is dependent on the HIV-1 codon usage and on the SLFN12 RNase active sites. Within HIV-1-infected individuals, SLFN12 expression in PBMCs correlated with HIV-1 plasma viral loads and proviral loads suggesting a link with the general activation of the immune system. Using an RNA FISH-Flow HIV-1 reactivation assay, we demonstrate that SLFN12 expression is enriched in infected cells positive for HIV-1 transcripts but negative for HIV-1 proteins. Thus, codon-usage dependent translation inhibition of HIV-1 proteins participates in HIV-1 latency and can restrict the amount of virus release after latency reversal.We thank Drs Yingying Li, Feng Gao and Beatrice H. Hahn for providing codon-optimized HIV-1 Gag expression vector, Drs James Hoxie and Susan Zolla-Pazner for supplying anti-Nef and -p24 antibodies, respectively through the NIH AIDS reagent program. We also thank Dr Song Gao for providing SLFN13-tRNA structure information, and Dr Maria-Eugenia Gas Lopez and Dr Ester Gea-Mallorquí for advise. This work was supported by following grants: M.K.I., JSPS Oversea Research Fellowship and Takeda Science Foundation; A.E.C., PT17/0009/0019 (ISCIII/MINECO and FEDER); M.J.B., RTI2018-101082-B-I00 and PID2021-123321OB-I00 [MINECO/FEDER]), and the Miguel Servet program by ISCIII (CP17/00179 and CPII22/00005); C.B., M.R.R., C.D.C., European Union’s Horizon 2020 research and innovation program under grant agreement 681137-EAVI2020 and NIH grant P01-AI131568; J.D., the Spanish Ministry of Science and Innovation (PID2019106959RB-I00/AEI/10.13039/501100011033); A.M., the Spanish Ministry of Science and Innovation (PID2019-106323RB-I00 AEI//10.13039/501100011033) and the institutional “María de Maeztu” Programme for Units of Excellence in R&D (CEX2018-000792-M).info:eu-repo/semantics/publishedVersio

Schlafen 12 restricts HIV-1 latency reversal by a codon-usage dependent post-transcriptional block in CD4+ T cells

Latency is a major barrier towards virus elimination in HIV-1-infected individuals. Yet, the mechanisms that contribute to the maintenance of HIV-1 latency are incompletely understood. Here we describe the Schlafen 12 protein (SLFN12) as an HIV-1 restriction factor that establishes a post-transcriptional block in HIV-1-infected cells and thereby inhibits HIV-1 replication and virus reactivation from latently infected cells. The inhibitory activity is dependent on the HIV-1 codon usage and on the SLFN12 RNase active sites. Within HIV-1-infected individuals, SLFN12 expression in PBMCs correlated with HIV-1 plasma viral loads and proviral loads suggesting a link with the general activation of the immune system. Using an RNA FISH-Flow HIV-1 reactivation assay, we demonstrate that SLFN12 expression is enriched in infected cells positive for HIV-1 transcripts but negative for HIV-1 proteins. Thus, codon-usage dependent translation inhibition of HIV-1 proteins participates in HIV-1 latency and can restrict the amount of virus release after latency reversal. In cell lines and HIV-1 patient PBMCs, the Schlafen 12 protein (SLFN12) is shown to be an HIV-1 restriction factor that inhibits HIV-1 replication and virus reactivatio

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

One of the key challenges when operating microcontrollers in harsh environments such as space is radiation-induced single event upsets (SEUs), which can lead to errors in computation. Common countermeasures rely on proprietary radiation-hardened technologies, low density technologies, or extensive replication, leading to high costs and low performance and efficiency. To combat this, we present Trikarenos, a fault-tolerant 32-bit RISC-V microcontroller SoC in an advanced TSMC 28nm technology. Trikarenos alleviates the replication cost by employing a configurable triple-core lockstep configuration, allowing three Ibex cores to execute applications reliably, operating on ECC-protected memory. If reliability is not needed for a given application, the cores can operate independently in parallel for higher performance and efficiency. Trikarenos consumes 15.7mW at 250MHz executing a fault-tolerant matrix-matrix multiplication, a 21.5x efficiency gain over state-of-the-art, and performance is increased by 2.96x when reliability is not needed for processing, with a 2.36x increase in energy efficiency

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

With the shrinking of technology nodes and the use of parallel processor clusters in hostile and critical environments, such as space, run-time faults caused by radiation are a serious cross-cutting concern, also impacting architectural design. This paper introduces an architectural approach to run-time configurable soft-error tolerance at the core level, augmenting a six-core open-source RISC-V cluster with a novel On-Demand Redundancy Grouping (ODRG) scheme. ODRG allows the cluster to operate either as two fault-tolerant cores, or six individual cores for high-performance, with limited overhead to switch between these modes during run-time. The ODRG unit adds less than 11% of a core's area for a three-core group, or a total of 1% of the cluster area, and shows negligible timing increase, which compares favorably to a commercial state-of-the-art implementation, and is 2.5$\times$ faster in fault recovery re-synchronization. Furthermore, unlike other implementations, when redundancy is not necessary, the ODRG approach allows the redundant cores to be used for independent computation, allowing up to 2.96$\times$ increase in performance for selected applications

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

ISSN:2378-9638ISSN:2378-962

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

With the shrinking of technology nodes and the use of parallel processor clusters in hostile and critical environments, such as space, run-time faults caused by radiation are a serious cross-cutting concern, also impacting architectural design. This paper introduces an architectural approach to run-time configurable soft-error tolerance at the core level, augmenting a six-core open-source RISC-V cluster with a novel On-Demand Redundancy Grouping (ODRG) scheme. ODRG allows the cluster to operate either as two fault-tolerant cores, or six individual cores for high-performance, with limited overhead to switch between these modes during run-time. The ODRG unit adds less than 11% of a core's area for a three-core group, or a total of 1% of the cluster area, and shows negligible timing increase, which compares favorably to a commercial state-of-the-art implementation, and is 2.5× faster in fault recovery re-synchronization. Furthermore, when redundancy is not necessary, the ODRG approach allows the redundant cores to be used for independent computation, allowing up to 2.96× increase in performance for selected applications